1. Field of the Invention
The present invention relates to digital communication systems.
2. Description of the Prior Art
Multi-lane digital communications systems allow computer processors to communicate with a variety of other devices in a highly flexible manner. Such systems employ a plurality of different data channels (sometimes referred to as “lanes”) that communicate with all of the devices in a network. A lane is a serial point-to-point connection that connects a “root” device to an “endpoint” device. The lanes can be configured as serial data channels, or they can be grouped together to act as parallel data busses, depending on the requirements of the specific device connected to the system.
One type of multi-lane digital communication system is referred to as “PCI Express.” PCI Express is a digital communications bus that allows expansion cards to be added to a computer system. PCI Express allows data transfer over 32 different lanes. Each PCI express Gen 1 lane allows a data transfer rate of 250 MB per second (thus the total data transfer rate for all lanes is 8 GB per second). PCI Express also includes a plurality of serial interconnects. A single hub with many pins connects a central unit (such as the mother board of a computer) to the PCI Express bus.
The PCI Express communications protocol is layered. The layers include a transaction layer, a data link layer; and a physical layer. The physical layer is divided into a logical sublayer and an electrical sublayer. The logical sublayer is frequently further divided into a physical coding sublayer (PCS) and a media access control (MAC) sublayer. In the electrical sublayer, each lane includes two unidirectional low voltage differential signaling (LVDS) conductor pairs that transmit data at 2.5 gigabits per second. Transmit and receive functions use different LDVS pairs, resulting in four conductors per lane.
PCI Express sends all control messages, including interrupts, over the same links used for data. Typically, the serial protocol can never be blocked. Data transmitted on multiple-lane links is interleaved so that each successive byte is transmitted on a different lane in a process referred to as “data striping.”
The Data Link Layer (DLL) sequences transaction layer packets (TLPs) that are generated by the transaction layer. The DLL also provides data protection via a 32-bit cyclic redundancy check code (referred to as “LCRC”) and an acknowledgement protocol. When a TLP passes an LCRC check and a sequence number check, an acknowledgement (ACK) is returned. When a TLP fails the LCRC check, a negative acknowledgement (NAK) is sent. TLPs that result in a NAK, or timeouts that occur while waiting for an ACK, result in the TLPs being replayed from a buffer in the transmit data path of the DLL. ACK and NAK signals are communicated via a low-level packet known as a data link layer packet, or DLLP. DLLPs are also used to communicate flow control information between the transaction layers of two connected devices, as well as some power management functions.
PCI Express is a High Performance/High Bandwidth protocol. However like many protocols, it suffers efficiency problems when transmitting small packets. Thus, to create a high performance design one must send large packets across the express link. At odds with this is the Cache line size in many processors so that many root ports only supported small packet sizes, which in turn has cause many devices to only support small packet sizes, reducing the performance characteristics of the protocol.
Current multi-lane systems require an address to be sent from the root device to the endpoint device each time a memory access occurs. However, many sequential accesses are to sequentially contiguous memory locations. For example, a first access might be to a first memory location, a next access might be to a memory location that is next to the first location. However, the root device will send an address during both memory accesses. The sending of the address can consume a substantial amount of time during a memory access, especially when many small packets are being accessed.
Therefore, there is a need for a system that eliminates the need for sending an address when accessing contiguous memory locations during subsequent memory accesses.